Interview questions

ORPIW20150131

1. D/W the following:
- Reg & logic
- UVM/OVM/VMM
- Verilog & SystemVerilog
- Generator & driver
- Sequencer & sequence
- Setup & hold time
- Rand & randc

2. Question on assoc array & dynamic array

3. Question on constraints
class test;

rand bit a;
bit b;

constraint c_a{a == 1;}

endclass: test

How can we randomize 'b'?

4. class test1;
rand int a;

constraint c_a {a == 5;}

endclass: test1

class test2
test1 t1 =new;

constraint c_a{a == 10;}
if(!(t1.randomize()))
 $display("t1.a = %d",t1.a);
else
$display("Randomization failed");

endclass: test2

What is the output of the program?

5.
a = [00,01]
b = [10];
c = [11];

Write covergroup for the above 3 variables.

6.
class test;
randc bit [1:0]a;
end class: test

program test_randc;

test t = new;

repeat (5) begin
$display("t.a = %d",t.a);
end

Will randc violate in this scenario?