Interview questions

SVT20150425

1. Replicate always logic inside program module
2. D/W
- Task & function
- Module & program block
- UVM & OVM
- Advantages of UVM over SV. Need for UVM
- Setup & hold time
- Casex & casez
- Blocking & non-blocking statements
- Inter and intra segment delays
- Config_db & resouce_db
- Initial & final block
- posedge & $rose
- Ignore & illegal bins
- Queue & mailbox
- Case equality & case inequality operator
- Assertions: -> & =>
3. Why do we need UVM factory?
4. What happens when we pass +UVM_TESTNAME= testcase from command line (explain the flow)
5. Explain communication b/w sequence -> sequencer -> driver
6. Need for interface and virtual interface
7. Explain race condition with example
8. Need for sequencer. What happens when we have just one sequence in our environment? Do we still need a sequencer
9. Phases in UVM, which of them are top-down/bottom-up.
10. What are the different ways of generating a clock
11. Write covergroup for a 32-bit address variable
12. Questions on overriding constraints in base class
13. Explain polymorphism with example
14. Different types of arrays
15. Usage of $stable, first_match in assertions
16. Question on TLM ports (analysis port/export/imp)
17. How is data driven into DUT in SV & UVM environment
18. What happens when only ## is passed in this case:
req -> ## grant
19. Which component/object do we code, coverage?

Interview questions

ORPIW20150131

1. D/W the following:
- Reg & logic
- UVM/OVM/VMM
- Verilog & SystemVerilog
- Generator & driver
- Sequencer & sequence
- Setup & hold time
- Rand & randc

2. Question on assoc array & dynamic array

3. Question on constraints
class test;

rand bit a;
bit b;

constraint c_a{a == 1;}

endclass: test

How can we randomize 'b'?

4. class test1;
rand int a;

constraint c_a {a == 5;}

endclass: test1

class test2
test1 t1 =new;

constraint c_a{a == 10;}
if(!(t1.randomize()))
 $display("t1.a = %d",t1.a);
else
$display("Randomization failed");

endclass: test2

What is the output of the program?

5.
a = [00,01]
b = [10];
c = [11];

Write covergroup for the above 3 variables.

6.
class test;
randc bit [1:0]a;
end class: test

program test_randc;

test t = new;

repeat (5) begin
$display("t.a = %d",t.a);
end

Will randc violate in this scenario?